<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2708876</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Sat Feb 25 21:38:06 2023</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2019.2 (64-bit)</TD>
  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>a9cb227d198841c3b3e41817676bda48</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>2</TD>
  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>c376a848caf654e3a5945f00df6df29d</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>c376a848caf654e3a5945f00df6df29d</TD>
  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7a35t</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>artix7</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>csg324</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i7-7500U CPU @ 2.70GHz</TD>
  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>2904 MHz</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Windows Server 2016 or Windows 10</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>4.000 GB</TD>
  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>abstractfileview_close=1</TD>
   <TD>abstractfileview_reload=1</TD>
   <TD>basedialog_cancel=2</TD>
   <TD>basedialog_ok=74</TD>
</TR><TR ALIGN='LEFT'>   <TD>basedialog_yes=8</TD>
   <TD>cmdmsgdialog_messages=3</TD>
   <TD>cmdmsgdialog_ok=8</TD>
   <TD>cmdmsgdialog_open_messages_view=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>constraintschooserpanel_add_files=4</TD>
   <TD>constraintschooserpanel_file_table=2</TD>
   <TD>coretreetablepanel_core_tree_table=7</TD>
   <TD>createconstraintsfilepanel_file_location=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>createconstraintsfilepanel_file_name=1</TD>
   <TD>customizecoredialog_ip_location=1</TD>
   <TD>customizecoredialog_switch_to_defaults=1</TD>
   <TD>customizeerrordialog_ok=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>filesetpanel_file_set_panel_tree=159</TD>
   <TD>filesetpanel_messages=1</TD>
   <TD>filtertoolbar_show_all=1</TD>
   <TD>flownavigatortreepanel_flow_navigator_tree=48</TD>
</TR><TR ALIGN='LEFT'>   <TD>fpgachooser_category=3</TD>
   <TD>fpgachooser_family=1</TD>
   <TD>fpgachooser_fpga_table=1</TD>
   <TD>fpgachooser_package=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>fpgachooser_speed=1</TD>
   <TD>gettingstartedview_create_new_project=1</TD>
   <TD>gettingstartedview_open_project=1</TD>
   <TD>hardwaredashboardview_show_dashboard_options=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>hardwaretreepanel_hardware_tree_table=2</TD>
   <TD>hpopuptitle_close=1</TD>
   <TD>mainmenumgr_file=2</TD>
   <TD>mainmenumgr_open_recent_project=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_project=1</TD>
   <TD>mainmenumgr_reports=6</TD>
   <TD>mainmenumgr_view=2</TD>
   <TD>mainmenumgr_window=14</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainwinmenumgr_layout=4</TD>
   <TD>msgtreepanel_message_severity=1</TD>
   <TD>msgtreepanel_message_view_tree=58</TD>
   <TD>msgview_clear_messages_resulting_from_user_executed=9</TD>
</TR><TR ALIGN='LEFT'>   <TD>msgview_critical_warnings=2</TD>
   <TD>msgview_error_messages=4</TD>
   <TD>msgview_information_messages=1</TD>
   <TD>msgview_warning_messages=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_add_module_to_bd=2</TD>
   <TD>pacommandnames_add_sources=7</TD>
   <TD>pacommandnames_auto_update_hier=23</TD>
   <TD>pacommandnames_log_window=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_message_window=1</TD>
   <TD>pacommandnames_open_hardware_manager=1</TD>
   <TD>pacommandnames_open_project=1</TD>
   <TD>pacommandnames_open_target_wizard=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_ports_window=3</TD>
   <TD>pacommandnames_program_fpga=2</TD>
   <TD>pacommandnames_reports_window=1</TD>
   <TD>pacommandnames_run_bitgen=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_schematic=1</TD>
   <TD>pacommandnames_set_as_top=2</TD>
   <TD>pacommandnames_simulation_live_break=1</TD>
   <TD>pacommandnames_simulation_live_run_all=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_simulation_run_behavioral=9</TD>
   <TD>paviews_code=4</TD>
   <TD>paviews_dashboard=1</TD>
   <TD>paviews_project_summary=5</TD>
</TR><TR ALIGN='LEFT'>   <TD>paviews_schematic=1</TD>
   <TD>programdebugtab_open_recently_opened_target=1</TD>
   <TD>programdebugtab_open_target=1</TD>
   <TD>programfpgadialog_program=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>progressdialog_cancel=2</TD>
   <TD>projectnamechooser_choose_project_location=1</TD>
   <TD>projectnamechooser_project_name=2</TD>
   <TD>projecttab_close_design=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>rdicommands_delete=8</TD>
   <TD>reportipstatusinfodialog_report_ip_status=1</TD>
   <TD>saveprojectutils_save=2</TD>
   <TD>signaltreepanel_signal_tree_table=51</TD>
</TR><TR ALIGN='LEFT'>   <TD>simpleoutputproductdialog_generate_output_products_immediately=5</TD>
   <TD>srcchooserpanel_add_directories=2</TD>
   <TD>srcchooserpanel_add_hdl_and_netlist_files_to_your_project=3</TD>
   <TD>srcchooserpanel_make_local_copy_of_these_files_into=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>srcchooserpanel_scan_and_add_rtl_include_files_into=1</TD>
   <TD>srcmenu_ip_documentation=2</TD>
   <TD>srcmenu_ip_hierarchy=22</TD>
   <TD>syntheticagettingstartedview_recent_projects=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>systemtreeview_system_tree=2</TD>
   <TD>taskbanner_close=2</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addmoduletoblockdesign=2</TD>
   <TD>addsources=8</TD>
   <TD>coreview=3</TD>
   <TD>createblockdesign=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>customizecore=3</TD>
   <TD>editdelete=8</TD>
   <TD>editundo=1</TD>
   <TD>launchopentarget=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>launchprogramfpga=2</TD>
   <TD>newproject=1</TD>
   <TD>openhardwaremanager=2</TD>
   <TD>openproject=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>openrecenttarget=1</TD>
   <TD>recustomizecore=5</TD>
   <TD>reportipstatus=1</TD>
   <TD>runbitgen=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>runimplementation=15</TD>
   <TD>runschematic=1</TD>
   <TD>runsynthesis=10</TD>
   <TD>savedesign=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>settopnode=2</TD>
   <TD>showview=17</TD>
   <TD>simulationbreak=1</TD>
   <TD>simulationrun=8</TD>
</TR><TR ALIGN='LEFT'>   <TD>simulationrunall=1</TD>
   <TD>toolssettings=1</TD>
   <TD>viewtaskimplementation=1</TD>
   <TD>viewtaskprojectmanager=2</TD>
</TR>  </TABLE>
</TR><TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>guimode=7</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>constraintsetcount=1</TD>
   <TD>core_container=false</TD>
   <TD>currentimplrun=impl_1</TD>
   <TD>currentsynthesisrun=synth_1</TD>
</TR><TR ALIGN='LEFT'>   <TD>default_library=xil_defaultlib</TD>
   <TD>designmode=RTL</TD>
   <TD>export_simulation_activehdl=4</TD>
   <TD>export_simulation_ies=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_modelsim=4</TD>
   <TD>export_simulation_questa=4</TD>
   <TD>export_simulation_riviera=4</TD>
   <TD>export_simulation_vcs=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_xsim=4</TD>
   <TD>implstrategy=Vivado Implementation Defaults</TD>
   <TD>launch_simulation_activehdl=0</TD>
   <TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_modelsim=0</TD>
   <TD>launch_simulation_questa=0</TD>
   <TD>launch_simulation_riviera=0</TD>
   <TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_xsim=8</TD>
   <TD>simulator_language=Mixed</TD>
   <TD>srcsetcount=138</TD>
   <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
</TR><TR ALIGN='LEFT'>   <TD>target_language=Verilog</TD>
   <TD>target_simulator=XSim</TD>
   <TD>totalimplruns=2</TD>
   <TD>totalsynthesisruns=2</TD>
</TR>  </TABLE>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=5</TD>
    <TD>carry4=393</TD>
    <TD>fdce=6197</TD>
    <TD>fdpe=387</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre=2748</TD>
    <TD>fdse=1</TD>
    <TD>gnd=138</TD>
    <TD>ibuf=22</TD>
</TR><TR ALIGN='LEFT'>    <TD>keeper=1</TD>
    <TD>ldce=8</TD>
    <TD>lut1=283</TD>
    <TD>lut2=847</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut3=1071</TD>
    <TD>lut4=1543</TD>
    <TD>lut5=2277</TD>
    <TD>lut6=5473</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv=1</TD>
    <TD>muxf7=524</TD>
    <TD>muxf8=128</TD>
    <TD>obuft=20</TD>
</TR><TR ALIGN='LEFT'>    <TD>pullup=3</TD>
    <TD>ramb36e1=32</TD>
    <TD>ramd32=24</TD>
    <TD>rams32=8</TD>
</TR><TR ALIGN='LEFT'>    <TD>vcc=396</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=5</TD>
    <TD>carry4=393</TD>
    <TD>fdce=6197</TD>
    <TD>fdpe=387</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre=2748</TD>
    <TD>fdse=1</TD>
    <TD>gnd=138</TD>
    <TD>ibuf=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>iobuf=20</TD>
    <TD>keeper=1</TD>
    <TD>ldce=8</TD>
    <TD>lut1=283</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut2=847</TD>
    <TD>lut3=1071</TD>
    <TD>lut4=1543</TD>
    <TD>lut5=2277</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut6=5473</TD>
    <TD>mmcme2_adv=1</TD>
    <TD>muxf7=524</TD>
    <TD>muxf8=128</TD>
</TR><TR ALIGN='LEFT'>    <TD>pullup=3</TD>
    <TD>ram32m=4</TD>
    <TD>ramb36e1=32</TD>
    <TD>vcc=396</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>power_opt_design</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options_spo</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-cell_types=default::all</TD>
    <TD>-clocks=default::[not_specified]</TD>
    <TD>-exclude_cells=default::[not_specified]</TD>
    <TD>-include_cells=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bram_ports_augmented=0</TD>
    <TD>bram_ports_newly_gated=0</TD>
    <TD>bram_ports_total=64</TD>
    <TD>flow_state=default</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_augmented=0</TD>
    <TD>slice_registers_newly_gated=0</TD>
    <TD>slice_registers_total=9331</TD>
    <TD>srls_augmented=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>srls_newly_gated=0</TD>
    <TD>srls_total=0</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>ip_statistics</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clk_wiz_v6_0_4_0_0/1</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>clkin1_period=10.000</TD>
    <TD>clkin2_period=10.000</TD>
    <TD>clock_mgr_type=NA</TD>
    <TD>component_name=PLL</TD>
</TR><TR ALIGN='LEFT'>    <TD>core_container=NA</TD>
    <TD>enable_axi=0</TD>
    <TD>feedback_source=FDBK_AUTO</TD>
    <TD>feedback_type=SINGLE</TD>
</TR><TR ALIGN='LEFT'>    <TD>iptotal=1</TD>
    <TD>manual_override=false</TD>
    <TD>num_out_clk=2</TD>
    <TD>primitive=MMCM</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_dyn_phase_shift=false</TD>
    <TD>use_dyn_reconfig=false</TD>
    <TD>use_inclk_stopped=false</TD>
    <TD>use_inclk_switchover=false</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_locked=true</TD>
    <TD>use_max_i_jitter=false</TD>
    <TD>use_min_o_jitter=false</TD>
    <TD>use_phase_alignment=true</TD>
</TR><TR ALIGN='LEFT'>    <TD>use_power_down=false</TD>
    <TD>use_reset=true</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-internal=default::[not_specified]</TD>
    <TD>-internal_only=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-name=default::[not_specified]</TD>
    <TD>-no_waivers=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
    <TD>-ruledecks=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-upgrade_cw=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufc-1=1</TD>
    <TD>cfgbvs-1=1</TD>
    <TD>check-3=1</TD>
    <TD>plck-12=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>reqp-1839=20</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufgctrl_available=32</TD>
    <TD>bufgctrl_fixed=0</TD>
    <TD>bufgctrl_used=5</TD>
    <TD>bufgctrl_util_percentage=15.63</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufhce_available=72</TD>
    <TD>bufhce_fixed=0</TD>
    <TD>bufhce_used=0</TD>
    <TD>bufhce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufio_available=20</TD>
    <TD>bufio_fixed=0</TD>
    <TD>bufio_used=0</TD>
    <TD>bufio_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufmrce_available=10</TD>
    <TD>bufmrce_fixed=0</TD>
    <TD>bufmrce_used=0</TD>
    <TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_available=20</TD>
    <TD>bufr_fixed=0</TD>
    <TD>bufr_used=0</TD>
    <TD>bufr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_available=5</TD>
    <TD>mmcme2_adv_fixed=0</TD>
    <TD>mmcme2_adv_used=1</TD>
    <TD>mmcme2_adv_util_percentage=20.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>plle2_adv_available=5</TD>
    <TD>plle2_adv_fixed=0</TD>
    <TD>plle2_adv_used=0</TD>
    <TD>plle2_adv_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>dsps_available=90</TD>
    <TD>dsps_fixed=0</TD>
    <TD>dsps_used=0</TD>
    <TD>dsps_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>blvds_25=0</TD>
    <TD>diff_hstl_i=0</TD>
    <TD>diff_hstl_i_18=0</TD>
    <TD>diff_hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_ii_18=0</TD>
    <TD>diff_hsul_12=0</TD>
    <TD>diff_mobile_ddr=0</TD>
    <TD>diff_sstl135=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl135_r=0</TD>
    <TD>diff_sstl15=0</TD>
    <TD>diff_sstl15_r=0</TD>
    <TD>diff_sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl18_ii=0</TD>
    <TD>hstl_i=0</TD>
    <TD>hstl_i_18=0</TD>
    <TD>hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>hstl_ii_18=0</TD>
    <TD>hsul_12=0</TD>
    <TD>lvcmos12=0</TD>
    <TD>lvcmos15=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvcmos18=0</TD>
    <TD>lvcmos25=0</TD>
    <TD>lvcmos33=1</TD>
    <TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvttl=0</TD>
    <TD>mini_lvds_25=0</TD>
    <TD>mobile_ddr=0</TD>
    <TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ppds_25=0</TD>
    <TD>rsds_25=0</TD>
    <TD>sstl135=0</TD>
    <TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl15=0</TD>
    <TD>sstl15_r=0</TD>
    <TD>sstl18_i=0</TD>
    <TD>sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>tmds_33=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>block_ram_tile_available=50</TD>
    <TD>block_ram_tile_fixed=0</TD>
    <TD>block_ram_tile_used=32</TD>
    <TD>block_ram_tile_util_percentage=64.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18_available=100</TD>
    <TD>ramb18_fixed=0</TD>
    <TD>ramb18_used=0</TD>
    <TD>ramb18_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36_fifo_available=50</TD>
    <TD>ramb36_fifo_fixed=0</TD>
    <TD>ramb36_fifo_used=32</TD>
    <TD>ramb36_fifo_util_percentage=64.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36e1_only_used=32</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg_functional_category=Clock</TD>
    <TD>bufg_used=5</TD>
    <TD>carry4_functional_category=CarryLogic</TD>
    <TD>carry4_used=393</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdce_functional_category=Flop &amp; Latch</TD>
    <TD>fdce_used=6195</TD>
    <TD>fdpe_functional_category=Flop &amp; Latch</TD>
    <TD>fdpe_used=387</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre_functional_category=Flop &amp; Latch</TD>
    <TD>fdre_used=2748</TD>
    <TD>fdse_functional_category=Flop &amp; Latch</TD>
    <TD>fdse_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf_functional_category=IO</TD>
    <TD>ibuf_used=22</TD>
    <TD>keeper_functional_category=Others</TD>
    <TD>keeper_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>ldce_functional_category=Flop &amp; Latch</TD>
    <TD>ldce_used=8</TD>
    <TD>lut1_functional_category=LUT</TD>
    <TD>lut1_used=260</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut2_functional_category=LUT</TD>
    <TD>lut2_used=851</TD>
    <TD>lut3_functional_category=LUT</TD>
    <TD>lut3_used=1067</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut4_functional_category=LUT</TD>
    <TD>lut4_used=1541</TD>
    <TD>lut5_functional_category=LUT</TD>
    <TD>lut5_used=2277</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut6_functional_category=LUT</TD>
    <TD>lut6_used=5473</TD>
    <TD>mmcme2_adv_functional_category=Clock</TD>
    <TD>mmcme2_adv_used=1</TD>
</TR><TR ALIGN='LEFT'>    <TD>muxf7_functional_category=MuxFx</TD>
    <TD>muxf7_used=524</TD>
    <TD>muxf8_functional_category=MuxFx</TD>
    <TD>muxf8_used=128</TD>
</TR><TR ALIGN='LEFT'>    <TD>obuft_functional_category=IO</TD>
    <TD>obuft_used=20</TD>
    <TD>pullup_functional_category=I/O</TD>
    <TD>pullup_used=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36e1_functional_category=Block Memory</TD>
    <TD>ramb36e1_used=32</TD>
    <TD>ramd32_functional_category=Distributed Memory</TD>
    <TD>ramd32_used=24</TD>
</TR><TR ALIGN='LEFT'>    <TD>rams32_functional_category=Distributed Memory</TD>
    <TD>rams32_used=8</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>f7_muxes_available=16300</TD>
    <TD>f7_muxes_fixed=0</TD>
    <TD>f7_muxes_used=524</TD>
    <TD>f7_muxes_util_percentage=3.21</TD>
</TR><TR ALIGN='LEFT'>    <TD>f8_muxes_available=8150</TD>
    <TD>f8_muxes_fixed=0</TD>
    <TD>f8_muxes_used=128</TD>
    <TD>f8_muxes_util_percentage=1.57</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=16</TD>
    <TD>lut_as_logic_available=20800</TD>
    <TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_used=10111</TD>
    <TD>lut_as_logic_util_percentage=48.61</TD>
    <TD>lut_as_memory_available=9600</TD>
    <TD>lut_as_memory_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_used=16</TD>
    <TD>lut_as_memory_util_percentage=0.17</TD>
    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_available=41600</TD>
    <TD>register_as_flip_flop_fixed=0</TD>
    <TD>register_as_flip_flop_used=9331</TD>
    <TD>register_as_flip_flop_util_percentage=22.43</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_latch_available=41600</TD>
    <TD>register_as_latch_fixed=0</TD>
    <TD>register_as_latch_used=8</TD>
    <TD>register_as_latch_util_percentage=0.02</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_luts_available=20800</TD>
    <TD>slice_luts_fixed=0</TD>
    <TD>slice_luts_used=10127</TD>
    <TD>slice_luts_util_percentage=48.69</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_available=41600</TD>
    <TD>slice_registers_fixed=0</TD>
    <TD>slice_registers_used=9339</TD>
    <TD>slice_registers_util_percentage=22.45</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=16</TD>
    <TD>lut_as_logic_available=20800</TD>
    <TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_used=10111</TD>
    <TD>lut_as_logic_util_percentage=48.61</TD>
    <TD>lut_as_memory_available=9600</TD>
    <TD>lut_as_memory_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_used=16</TD>
    <TD>lut_as_memory_util_percentage=0.17</TD>
    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_in_front_of_the_register_is_unused_fixed=0</TD>
    <TD>lut_in_front_of_the_register_is_unused_used=3821</TD>
    <TD>lut_in_front_of_the_register_is_used_fixed=3821</TD>
    <TD>lut_in_front_of_the_register_is_used_used=2999</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_driven_from_outside_the_slice_fixed=2999</TD>
    <TD>register_driven_from_outside_the_slice_used=6820</TD>
    <TD>register_driven_from_within_the_slice_fixed=6820</TD>
    <TD>register_driven_from_within_the_slice_used=2519</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_available=8150</TD>
    <TD>slice_fixed=0</TD>
    <TD>slice_registers_available=41600</TD>
    <TD>slice_registers_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_used=9339</TD>
    <TD>slice_registers_util_percentage=22.45</TD>
    <TD>slice_used=3853</TD>
    <TD>slice_util_percentage=47.28</TD>
</TR><TR ALIGN='LEFT'>    <TD>slicel_fixed=0</TD>
    <TD>slicel_used=2717</TD>
    <TD>slicem_fixed=0</TD>
    <TD>slicem_used=1136</TD>
</TR><TR ALIGN='LEFT'>    <TD>unique_control_sets_available=8150</TD>
    <TD>unique_control_sets_fixed=8150</TD>
    <TD>unique_control_sets_used=439</TD>
    <TD>unique_control_sets_util_percentage=5.39</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_and_o6_fixed=5.39</TD>
    <TD>using_o5_and_o6_used=16</TD>
    <TD>using_o5_output_only_fixed=16</TD>
    <TD>using_o5_output_only_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o6_output_only_fixed=0</TD>
    <TD>using_o6_output_only_used=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bscane2_available=4</TD>
    <TD>bscane2_fixed=0</TD>
    <TD>bscane2_used=0</TD>
    <TD>bscane2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>capturee2_available=1</TD>
    <TD>capturee2_fixed=0</TD>
    <TD>capturee2_used=0</TD>
    <TD>capturee2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>dna_port_available=1</TD>
    <TD>dna_port_fixed=0</TD>
    <TD>dna_port_used=0</TD>
    <TD>dna_port_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>efuse_usr_available=1</TD>
    <TD>efuse_usr_fixed=0</TD>
    <TD>efuse_usr_used=0</TD>
    <TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_available=1</TD>
    <TD>frame_ecce2_fixed=0</TD>
    <TD>frame_ecce2_used=0</TD>
    <TD>frame_ecce2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>icape2_available=2</TD>
    <TD>icape2_fixed=0</TD>
    <TD>icape2_used=0</TD>
    <TD>icape2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcie_2_1_available=1</TD>
    <TD>pcie_2_1_fixed=0</TD>
    <TD>pcie_2_1_used=0</TD>
    <TD>pcie_2_1_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>startupe2_available=1</TD>
    <TD>startupe2_fixed=0</TD>
    <TD>startupe2_used=0</TD>
    <TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_available=1</TD>
    <TD>xadc_fixed=0</TD>
    <TD>xadc_used=0</TD>
    <TD>xadc_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-assert=default::[not_specified]</TD>
    <TD>-bufg=default::12</TD>
    <TD>-cascade_dsp=default::auto</TD>
    <TD>-constrset=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-control_set_opt_threshold=default::auto</TD>
    <TD>-directive=default::default</TD>
    <TD>-fanout_limit=default::10000</TD>
    <TD>-flatten_hierarchy=default::rebuilt</TD>
</TR><TR ALIGN='LEFT'>    <TD>-fsm_extraction=default::auto</TD>
    <TD>-gated_clock_conversion=default::off</TD>
    <TD>-generic=default::[not_specified]</TD>
    <TD>-include_dirs=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-keep_equivalent_registers=default::[not_specified]</TD>
    <TD>-max_bram=default::-1</TD>
    <TD>-max_bram_cascade_height=default::-1</TD>
    <TD>-max_dsp=default::-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_uram=default::-1</TD>
    <TD>-max_uram_cascade_height=default::-1</TD>
    <TD>-mode=default::default</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_lc=default::[not_specified]</TD>
    <TD>-no_srlextract=default::[not_specified]</TD>
    <TD>-no_timing_driven=default::[not_specified]</TD>
    <TD>-part=xc7a35tcsg324-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-resource_sharing=default::auto</TD>
    <TD>-retiming=default::[not_specified]</TD>
    <TD>-rtl=default::[not_specified]</TD>
    <TD>-rtl_skip_constraints=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-rtl_skip_ip=default::[not_specified]</TD>
    <TD>-seu_protect=default::none</TD>
    <TD>-sfcu=default::[not_specified]</TD>
    <TD>-shreg_min_size=default::3</TD>
</TR><TR ALIGN='LEFT'>    <TD>-top=aic_rv32</TD>
    <TD>-verilog_define=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>elapsed=00:10:13s</TD>
    <TD>hls_ip=0</TD>
    <TD>memory_gain=1856.906MB</TD>
    <TD>memory_peak=2365.602MB</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-sim_mode=default::behavioral</TD>
    <TD>-sim_type=default::</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
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